1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, embodiments of this invention relate to the field of clock control of a multiple clock domain data processor and in particular clock control during scan testing of a multiple clock domain data processing system.
2. Description of the Prior Art
The scan testing of data processing circuits is known. Generally a test pattern is shifted into the processor via scan chains, the test is applied to the circuit for a predetermined number of functional clock pulses and the state of the processor after test is captured. Generally, the test patterns need to be input at a slow clock speed, and the output state of the processor needs to be clocked out at a slow clock speed. However, if it is required to test the operation of the circuit at an operational clocking speed then the circuit needs to be driven by clock pulses at this frequency. Where the clock is input externally to the core this is not a problem. However, in a processor core having multiple clock domains where the clock signals are generated by, for example, a PLL which can not be directly controlled at a top level interface of the chip it can be very difficult to control the different domains separately and enable the test patterns to be input, the test to be performed at speed and then the data to be extracted or captured.